Title: Progress in A Novel Architecture for High Performance Processing
Authors: Zhang, ZW; Liu, M; Liu, ZJ; Du, XL; Xie, SL; Ma, H; Ding, GX; Ren, WL; Zhou, FB; Sun, WQ; Wang, HJ; Wang, DL
Author Full Names: Zhang, Zhiwei; Liu, Meng; Liu, Zijun; Du, Xueliang; Xie, Shaolin; Ma, Hong; Ding, Guangxin; Ren, Weili; Zhou, Fabiao; Sun, Wenqin; Wang, Huijuan; Wang, Donglin
Source: JAPANESE JOURNAL OF APPLIED PHYSICS, 57 (4):SI 10.7567/JJAP.57.04FA03 APR 2018
Abstract: The high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance. It is suitable for data intensive applications like supercomputing, machine learning and wireless communication. An example chip with four application-specific integrated circuit (ASIC) cores which is the first generation of HPP cores has been taped out successfully under Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm low power process. The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU). Compared with MaPU, HPP has made great improvement in architecture. The chip with 32 HPP cores is being developed under TSMC 16 nm field effect transistor (FFC) technology process and is planed to use commercially. The peak performance of this chip can reach 4.3 teraFLOPS (TFLOPS) and its power efficiency is up to 89.5 gigaFLOPS per watt (GFLOPS/W). (C) 2018 The Japan Society of Applied Physics.
Article Number: 04FA03
IDS Number: GE1MV
Unique ID: WOS:000430981800004